In a conventional computer system memory architecture, one or more processors and any peripheral bus masters on a bus interconnect can request and obtain access to system memory (also called “M2 memory”), i.e., read from or write to the memory. Peripheral masters include external device controllers such as Peripheral Component Interconnect (PCI), PCI Express (PCIe), Serial Rapid Input/Output (SRIO) and Gigabit Ethernet® (GbE) controllers, to name just a few.
A secure system is defined as a system in which only processors and peripherals that have security clearance can gain access to the contents (e.g., computer instructions or the data with which such instructions operate) stored in secure memory. In a secure system, all processors and peripherals that do not have security clearance are denied access to those secure locations. A problem in trying to design a secure system with system memory is that when the system has a reset applied to it, the contents of the system memory are not reset (cleared). This could allow an unsecure processor or bus master, including one temporarily plugged into an external device controller of the system, to gain unauthorized access to the contents of the system memory.